This invention relates to semiconductor devices and their manufacture and, more particularly, to such devices incorporating, and processes for developing, capacitors at or near the interconnect level.
The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, such as p-channel MOS (PMOS), n-channel MOS (NMOS) and complimentary MOS (CMOS) transistors, bipolar transistors, and BiCMOS transistors.
Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active and passive devices are formed. The particular structure of a given active device can vary between device types. For example, in MOS transistors, an active device generally includes source and drain regions and a gate electrode that modulates current between the source and drain regions. Passive on-chip devices, such as capacitors and resistors, are typically strategically placed to interact with the active devices.
One important step in the manufacture of such devices is the formation of capacitors as a closely integrated part of the semiconductor device. Passive on-chip capacitors are desirable components for analog or mixed-signal circuit designs. In a CMOS based technology, capacitors are generally made using the MOS gate itself, with poly and substrate acting as the two electrodes and gate oxide as the dielectric.
There are at least two drawbacks of such gate capacitors. First, gate capacitors directly use the silicon real estate and thus increase the chip size and cost. Second, gate capacitors are not inherently passive, since the capacitance is dependent on the gate voltage the capacitance value may vary. Alternatively, capacitors could be made at the interconnect levels, where there often are spaces to accommodate extra elements without increasing the silicon area. Capacitors made of metal pieces would be truly passive with constant values. One possible structure of interconnect capacitance consists of two parallel metal lines with dielectric between them. A problem with this approach is that the spacing between two metal lines generally has a minimum value defined by the process technology. Disadvantageous to the relatively small chip area, without reducing the inter-metal spacing, long metal lines have been typically required to achieve sufficient capacitance values.
Accordingly, there is a need for semiconductor structures, and manufacturing processes therefor, that overcome the aforementioned disadvantages of the prior art.
According to various aspects of the present invention, embodiments thereof are exemplified in the form of semiconductor manufacturing processes for developing capacitors in compact areas such as at or near the interconnect level. One specific implementation directed to such manufacture begins with a substrate having first and second conductors separated by a temporary material. The material that separates the first and second conductors is removed and a trench therebetween is formed. A first material, having a relatively high dielectric constant (e.g., higher than about 7.0) is deposited over the substrate so that first material covers the trench and the first and second conductors adjacent to the trench. A second material, including metal, is then deposited over the first material so that it covers the first material above the trench and the first and second conductors adjacent to the trench. The second material is removed, for example, by a selective etch process, and, while removing the second material, the first material is detected for termination of the removal or etching of the second material.
Another related process, also according to the present invention, includes: a starting structure prepared in a Damascene process consisting of metal lines with oxide filling the gaps. A commonly-used new planarization process in semiconductor device manufacturing is chemical-mechanical polishing, or CMP. CMP is useful in the planarization of silicon wafers and of VLSI circuits between different manufacturing processes. CMP is used in this application to remove metal over the field. A selective etch process is then performed to remove the oxide deposited between the metal lines over the area where the capacitor is to be made. Photolithography, a process involving the photographic transfer of a pattern to a surface for etching, masks all outside areas to prevent the circuit from being damaged. A dielectric of silicon nitride is then deposited on the surface, forming a thin nitride layer on the sidewall of the metal lines. Silicon nitride has a high dielectric constant xe2x80x9ckxe2x80x9d (about 7.5) enabling capacitor formation. Blanket metal deposition follows the deposit of the dielectric and fills the newly formed gaps. A CMP process is again used to remove metal over the field. Because silicon nitride acts as a natural CMP etch-stopper, the other areas of the interconnects are protected by possible damage done during this process.
In another example embodiment, the capacitors are made more efficient by cross-coupling the two finger structures where both sides of a meta For example, in a specific implementation, this approach includes manufacturing a semiconductor device by providing a substrate having first and second metal conductors separated by a dielectric and arranged so that they are cross-coupled, with each of the first and second metal conductors including first and second surface sides facing the dielectric. Subsequent steps include: removing the dielectric that separates the first and second metal conductors and forming a trench therebetween; depositing a first material (such as silicon nitride), having a dielectric constant at least about 7.5, over the substrate so that first material covers the trench and the first and second metal conductors adjacent to the trench; depositing a second material, including metal, over the first material so that the second material covers the first material above the trench and the first and second metal conductors adjacent to the trench; removing the second material; and, while removing the second material, detecting the first material for terminating the removal of the second material.
In a more specific implementation, the first and second metal conductors form outside terminals of a two-capacitor structure, with the other material forming a common terminal interconnecting the two capacitors. The first material dielectrically separates the adjacent conductive areas that are used as the terminals.
In another more specific implementation, the first and second metal conductors form one terminal of a two-terminal capacitor structure, with the other material forming the other of the two terminals. The two terminals are dielectrically separated by the first material.
In one particular implementation found to be especially useful for a typical 0.20 micron technology, the first material is silicon nitride and removing the second material includes a selective etch process.
The above summary is not intended to provide an overview of all aspects of the present invention. Other aspects of the present invention are exemplified and described in connection with the detailed description.